In many current semiconductor integrated circuit (IC) systems, memory access and processing delays on paths in the IC systems are more and more dominated by the routing of electrical connections within the IC systems. For example, when relatively large memories are included within an IC system, these large memories are often implemented using multiple memory banks where wire lengths become long and eventually require registers to break access timing. In addition, existing on-die memory accesses typically require the same latency for all memory banks within such large system memories. As such, access latency typically increases with memory size as the number of clock cycles used for memory accesses are typically selected to cover the maximum access latency experienced for the different memory banks. Further, a system memory (e.g., system random access memory (RAM)) and related memory controller often serve many bus masters within the IC system, and the memory controller often includes many bus ports to the bus masters and many access ports to the system memory in order to allow parallel access by the bus masters to the system memory. As the complexities of such IC systems increase, the access logic also becomes more complex, and maximum access latency for the system memory increases significantly. As a result, system performance suffers due to increased access latency as the number of bus ports and the number of memory access ports increase with larger IC systems.